library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity seven_seg_driver is
	port(
		BCD_digit   : in  std_logic_vector(11 downto 0);
		clk         : in  std_logic;    --system clock
		rst         : in  std_logic;
		Sign        : in  std_logic;
		Overflow    : in  std_logic;
		DIGIT_ANODE : out std_logic_vector(3 downto 0);
		SEGMENT     : out std_logic_vector(6 downto 0)
	);
end seven_seg_driver;

architecture behavioral of seven_seg_driver is

-- Define the signals here if any.


begin

-- Develope your code here.


end behavioral;